1. Field of the Invention
The present invention relates to a row decoder for a semiconductor memory device, and more particularly, it relates to a row decoder for a semiconductor memory device of high efficiency which can provide both minimal power consumption and high-speed performance.
2. Discussion of Related Art
Row decoders are widely used for memory circuits and various parts, and are of importance in semiconductor devices. Accordingly, it is desirable that they have a power-saving function for minimizing power consumption and at the same time, offer high-speed performance. Research and development efforts have thus been devoted to the fabrication of such row decoders.
Referring to FIG. 1, a conventional row decoder is now described.
The conventional row decoder includes first to eighth selection line decoders, 1 to 8, each having: a pair of four-input NAND gates, NAND11, NAND12 to NAND81, NAND82; a word line decoder 9 having sixteen four-input NAND gates, NAND9-1 to NAND9-16; and eight cell strings ST1 to ST8 receiving output signals SL0, SL1 to SL14, SL15 of each NAND gate, NAND11, 12 to NAND81, and output signals, WL0 to WL15, of each of the NAND gates, NAND9-1 to NAND9-16.
Output signals, SL0, SL1 to SL14, SL15 of the selection line decoders, 1 to 8, are each used for selecting one of corresponding cell strings, ST1 to ST8. Word-line selection signals, WL0 to WL15, are each used for selecting and driving a corresponding memory cell's word line of the memory cells in the cell strings, ST1 to ST8. That is, the four-input NAND gates, NAND11, NAND12 to NAND81, NAND82, each apply an output signal to the first to eighth cell strings, ST1 to ST8, thus selecting one of the first to eighth cell strings, ST1 to ST8. In the meantime, NAND gates, NAND9-1 to NAND9-16, of word line decoder 9 each have output terminals corresponding to the respective input terminals of cell strings, ST1 to ST8, for receiving word-line selection signals WL0 to WL15.
According to the above-described construction, each output signal of the sixteen NAND gates, NAND9-1 to NAND9-16, of the word line decoder 9 actuates word lines of all cell strings, ST1 to ST8, that are selected or not selected by each output signal of four-input NAND gates, NAND11, NAND12 to NAND81, NAND82.
As described above, since one output signal of the word line decoder 9 actuates the word lines of the eight cell strings, a heavy load is applied onto the row decoder, thus retarding the row decoder performance. Furthermore, a buffer of large size must be used in order to increase fan-out, i.e. in order to let the row decoder have a large driving capability, which causes an increase in power consumption.